substitute command in vi

:%s/to_be_replaced/new/g

Waveform generation and view

To dump the waveform file

Add the following lines in verilog scripts.
$dumpfile("waveform.vcd");
$dumpvars(0, top_module_name);
0--hierarchical level. If sub-modules are included, increase the number.

To view the waveform
1) use DVE, command "dve &"
2) use Virsim command "vcs -RPP"

Translate gate-level script to transistor level

Use Mentor Calibre tool
Command: v2lvs -v counter.v -o counter.sp -i
"Using -i to Generate Simulation Output".

Scan insertion using design (DFT) compiler

If the script is optimized gate-level design go with the following:
Constraint-Optimized Scan Insertion Flow under dc_shell
1) select scan style (command: test_default_scan_style style multiplexed_flip_flop)
2) read design description (command: read_verilog)
3) define test protocol (command: set_dft_signal)
4) analyze nonscan design (command: dft_drc)
5) Insert scan cells (command: insert_dft)

Basic Scan Insertion Script
current_design Top
dft_drc
set_dft_configuration -fix_clock enable -fix_set enable \
-fix_reset enable
set_scan_configuration -chain_count
create_test_protocol -infer_clock -infer_async
preview_dft
insert_dft
dft_drc -coverage_estimate
report_scan_path -v exist -chain all
report_constraints -all_violators

If it is unmapped design, i.e., at the RT-level, use test-ready compile.

MAC address

Every network interface card (NIC) produced in the world has its own unique MAC address. A MAC address is made up of 6 sets of hexadecimal numbers (two-characters each), e.g. A1:B2:C3:D4:E5:F6

BGA component

BGA stands for Ball Grid Array. A web definition from PrincetonUSA explains it as, "A type of memory chip with solder balls on the underside for mounting. Use of BGA allows die package size to be reduced because there is more surface area for attachment. Smaller packaging allows more components to be mounted on a module, making greater densities available. The smaller package also improves heat dissipation for better performance".

Hspice multiplicity

Given a component with a multiplicity value M , the simulator treats this component as if there were M such components all connected in parallel.