SVN commands

Check out the file
svn co https://victorio.uit.no/langtech/trunk main --username
... where you have replaced with the username you have aquired from the admin. This will enable you to check in your work. If you don't have a user name or just want to browse our code, just skip the username.
Update your working copy
svn up
Scedule a file for addition
svn add filename
Scedule a file for deletion
svn delete filename
You may also copy and move files and directories with these two commands, but read about them in the svn book first:
svn copy filename
svn move filename
Examine your changes
svn status
Examine the file history
svn log FILE
Change the commit message for a specific revision
svn propedit svn:log --revprop -r REV FILE
This will bring up the existing log text for the specified revision in your default editor (typically Emacs), where you can edit and change it as you want. This is useful if you accidentally committed some changes with an empty or uninformative log message.
Compare your modified file to the version in the repository
svn diff FILE
Compare some earlier versions, say here versions 123 and 120
svn diff -r 123:120 FILE
Undo your local changes (ie revert to the repository status)
svn revert FILE
Resolve Conflicts (Merge Others' Changes)
svn update
svn resolved
Commit your changes
svn ci -m "Your description of the changes here." FILE
(Note that the above changes, add, delete, copy, move, must all be committed by ci in order to take effect)

substitute command in vi

:%s/to_be_replaced/new/g

Waveform generation and view

To dump the waveform file

Add the following lines in verilog scripts.
$dumpfile("waveform.vcd");
$dumpvars(0, top_module_name);
0--hierarchical level. If sub-modules are included, increase the number.

To view the waveform
1) use DVE, command "dve &"
2) use Virsim command "vcs -RPP"

Translate gate-level script to transistor level

Use Mentor Calibre tool
Command: v2lvs -v counter.v -o counter.sp -i
"Using -i to Generate Simulation Output".

Scan insertion using design (DFT) compiler

If the script is optimized gate-level design go with the following:
Constraint-Optimized Scan Insertion Flow under dc_shell
1) select scan style (command: test_default_scan_style style multiplexed_flip_flop)
2) read design description (command: read_verilog)
3) define test protocol (command: set_dft_signal)
4) analyze nonscan design (command: dft_drc)
5) Insert scan cells (command: insert_dft)

Basic Scan Insertion Script
current_design Top
dft_drc
set_dft_configuration -fix_clock enable -fix_set enable \
-fix_reset enable
set_scan_configuration -chain_count
create_test_protocol -infer_clock -infer_async
preview_dft
insert_dft
dft_drc -coverage_estimate
report_scan_path -v exist -chain all
report_constraints -all_violators

If it is unmapped design, i.e., at the RT-level, use test-ready compile.

MAC address

Every network interface card (NIC) produced in the world has its own unique MAC address. A MAC address is made up of 6 sets of hexadecimal numbers (two-characters each), e.g. A1:B2:C3:D4:E5:F6

BGA component

BGA stands for Ball Grid Array. A web definition from PrincetonUSA explains it as, "A type of memory chip with solder balls on the underside for mounting. Use of BGA allows die package size to be reduced because there is more surface area for attachment. Smaller packaging allows more components to be mounted on a module, making greater densities available. The smaller package also improves heat dissipation for better performance".