Translate gate-level script to transistor level

Use Mentor Calibre tool
Command: v2lvs -v counter.v -o counter.sp -i
"Using -i to Generate Simulation Output".

Scan insertion using design (DFT) compiler

If the script is optimized gate-level design go with the following:
Constraint-Optimized Scan Insertion Flow under dc_shell
1) select scan style (command: test_default_scan_style style multiplexed_flip_flop)
2) read design description (command: read_verilog)
3) define test protocol (command: set_dft_signal)
4) analyze nonscan design (command: dft_drc)
5) Insert scan cells (command: insert_dft)

Basic Scan Insertion Script
current_design Top
dft_drc
set_dft_configuration -fix_clock enable -fix_set enable \
-fix_reset enable
set_scan_configuration -chain_count
create_test_protocol -infer_clock -infer_async
preview_dft
insert_dft
dft_drc -coverage_estimate
report_scan_path -v exist -chain all
report_constraints -all_violators

If it is unmapped design, i.e., at the RT-level, use test-ready compile.